DPDK
21.11.6
lib
pci
rte_pci.h
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2015 Intel Corporation.
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* Copyright 2013-2014 6WIND S.A.
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*/
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#ifndef _RTE_PCI_H_
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#define _RTE_PCI_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#include <stdio.h>
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#include <limits.h>
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#include <inttypes.h>
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#include <sys/types.h>
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/*
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* Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
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* configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
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* configuration space.
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*/
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#define RTE_PCI_CFG_SPACE_SIZE 256
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#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
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#define RTE_PCI_VENDOR_ID 0x00
/* 16 bits */
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#define RTE_PCI_DEVICE_ID 0x02
/* 16 bits */
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#define RTE_PCI_COMMAND 0x04
/* 16 bits */
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/* PCI Command Register */
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#define RTE_PCI_COMMAND_MASTER 0x4
/* Bus Master Enable */
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/* PCI Express capability registers */
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#define RTE_PCI_EXP_DEVCTL 8
/* Device Control */
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/* Extended Capabilities (PCI-X 2.0 and Express) */
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#define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
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#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
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#define RTE_PCI_EXT_CAP_ID_ERR 0x01
/* Advanced Error Reporting */
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#define RTE_PCI_EXT_CAP_ID_DSN 0x03
/* Device Serial Number */
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#define RTE_PCI_EXT_CAP_ID_SRIOV 0x10
/* SR-IOV*/
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/* Single Root I/O Virtualization */
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#define RTE_PCI_SRIOV_CAP 0x04
/* SR-IOV Capabilities */
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#define RTE_PCI_SRIOV_CTRL 0x08
/* SR-IOV Control */
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#define RTE_PCI_SRIOV_INITIAL_VF 0x0c
/* Initial VFs */
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#define RTE_PCI_SRIOV_TOTAL_VF 0x0e
/* Total VFs */
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#define RTE_PCI_SRIOV_NUM_VF 0x10
/* Number of VFs */
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#define RTE_PCI_SRIOV_FUNC_LINK 0x12
/* Function Dependency Link */
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#define RTE_PCI_SRIOV_VF_OFFSET 0x14
/* First VF Offset */
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#define RTE_PCI_SRIOV_VF_STRIDE 0x16
/* Following VF Stride */
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#define RTE_PCI_SRIOV_VF_DID 0x1a
/* VF Device ID */
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#define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c
/* Supported Page Sizes */
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#define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
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#define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
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#define PCI_SHORT_PRI_FMT "%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
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#define PCI_FMT_NVAL 4
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#define PCI_RESOURCE_FMT_NVAL 3
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#define PCI_MAX_RESOURCE 6
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struct
rte_pci_id
{
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uint32_t
class_id
;
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uint16_t
vendor_id
;
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uint16_t
device_id
;
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uint16_t
subsystem_vendor_id
;
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uint16_t
subsystem_device_id
;
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};
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struct
rte_pci_addr
{
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uint32_t
domain
;
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uint8_t
bus
;
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uint8_t
devid
;
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uint8_t
function
;
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};
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#define RTE_PCI_ANY_ID (0xffff)
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#define PCI_ANY_ID RTE_DEPRECATED(PCI_ANY_ID) RTE_PCI_ANY_ID
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#define RTE_CLASS_ANY_ID (0xffffff)
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void
rte_pci_device_name
(
const
struct
rte_pci_addr
*addr,
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char
*output,
size_t
size);
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int
rte_pci_addr_cmp
(
const
struct
rte_pci_addr
*addr,
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const
struct
rte_pci_addr
*addr2);
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int
rte_pci_addr_parse
(
const
char
*str,
struct
rte_pci_addr
*addr);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* _RTE_PCI_H_ */
rte_pci_id
Definition:
rte_pci.h:82
rte_pci_addr_parse
int rte_pci_addr_parse(const char *str, struct rte_pci_addr *addr)
rte_pci_id::device_id
uint16_t device_id
Definition:
rte_pci.h:85
rte_pci_id::class_id
uint32_t class_id
Definition:
rte_pci.h:83
rte_pci_addr
Definition:
rte_pci.h:93
rte_pci_addr::devid
uint8_t devid
Definition:
rte_pci.h:96
rte_pci_id::subsystem_vendor_id
uint16_t subsystem_vendor_id
Definition:
rte_pci.h:86
rte_pci_addr::bus
uint8_t bus
Definition:
rte_pci.h:95
rte_pci_addr::domain
uint32_t domain
Definition:
rte_pci.h:94
rte_pci_device_name
void rte_pci_device_name(const struct rte_pci_addr *addr, char *output, size_t size)
rte_pci_addr_cmp
int rte_pci_addr_cmp(const struct rte_pci_addr *addr, const struct rte_pci_addr *addr2)
rte_pci_id::vendor_id
uint16_t vendor_id
Definition:
rte_pci.h:84
rte_pci_id::subsystem_device_id
uint16_t subsystem_device_id
Definition:
rte_pci.h:87
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