21 #include <rte_compat.h>
50 RTE_PMD_I40E_PKG_OP_UNDEFINED = 0,
54 RTE_PMD_I40E_PKG_OP_MAX = 32
61 RTE_PMD_I40E_PKG_INFO_UNDEFINED = 0,
62 RTE_PMD_I40E_PKG_INFO_GLOBAL_HEADER,
63 RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES_SIZE,
64 RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES,
65 RTE_PMD_I40E_PKG_INFO_GLOBAL_MAX = 1024,
66 RTE_PMD_I40E_PKG_INFO_HEADER,
67 RTE_PMD_I40E_PKG_INFO_DEVID_NUM,
68 RTE_PMD_I40E_PKG_INFO_DEVID_LIST,
69 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM,
70 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST,
71 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM,
72 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST,
73 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM,
74 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST,
75 RTE_PMD_I40E_PKG_INFO_MAX = (int)0xFFFFFFFF
82 RTE_PMD_I40E_RSS_QUEUE_REGION_UNDEFINED,
103 RTE_PMD_I40E_RSS_QUEUE_REGION_INFO_GET,
104 RTE_PMD_I40E_RSS_QUEUE_REGION_OP_MAX
107 #define RTE_PMD_I40E_DDP_NAME_SIZE 32
108 #define RTE_PMD_I40E_PCTYPE_MAX 64
109 #define RTE_PMD_I40E_REGION_MAX_NUM 8
110 #define RTE_PMD_I40E_MAX_USER_PRIORITY 8
127 uint32_t vendor_dev_id;
128 uint32_t sub_vendor_dev_id;
139 uint8_t name[RTE_PMD_I40E_DDP_NAME_SIZE];
142 #define RTE_PMD_I40E_DDP_OWNER_UNKNOWN 0xFF
152 #define RTE_PMD_I40E_PROTO_NUM 6
153 #define RTE_PMD_I40E_PROTO_UNUSED 0xFF
160 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
168 uint8_t protocols[RTE_PMD_I40E_PROTO_NUM];
176 #define RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK 0x80000000
178 struct rte_pmd_i40e_ptype_mapping {
203 struct rte_pmd_i40e_queue_region_info {
207 uint8_t queue_start_index;
211 uint8_t user_priority_num;
213 uint8_t user_priority[RTE_PMD_I40E_MAX_USER_PRIORITY];
215 uint8_t flowtype_num;
221 uint8_t hw_flowtype[RTE_PMD_I40E_PCTYPE_MAX];
224 struct rte_pmd_i40e_queue_regions {
226 uint16_t queue_region_number;
227 struct rte_pmd_i40e_queue_region_info
228 region[RTE_PMD_I40E_REGION_MAX_NUM];
235 RTE_PMD_I40E_PKT_TEMPLATE_ACCEPT,
236 RTE_PMD_I40E_PKT_TEMPLATE_REJECT,
237 RTE_PMD_I40E_PKT_TEMPLATE_PASSTHRU,
298 enum rte_pmd_i40e_inset_type {
305 struct rte_pmd_i40e_inset_mask {
310 struct rte_pmd_i40e_inset {
312 struct rte_pmd_i40e_inset_mask mask[2];
577 uint64_t vf_mask, uint8_t on);
753 uint8_t *info, uint32_t size,
790 struct rte_pmd_i40e_ptype_mapping *mapping_items,
821 struct rte_pmd_i40e_ptype_mapping *mapping_items,
865 #define RTE_PMD_I40E_PCTYPE_MAX 64
866 #define RTE_PMD_I40E_FLOW_TYPE_MAX 64
868 struct rte_pmd_i40e_flow_type_mapping {
892 struct rte_pmd_i40e_flow_type_mapping *mapping_items,
909 struct rte_pmd_i40e_flow_type_mapping *mapping_items);
949 int rte_pmd_i40e_cfg_hash_inset(uint16_t port,
950 uint64_t pctype, uint64_t inset);
970 struct rte_pmd_i40e_inset *inset,
971 enum rte_pmd_i40e_inset_type inset_type);
991 struct rte_pmd_i40e_inset *inset,
992 enum rte_pmd_i40e_inset_type inset_type);
1013 bit_idx = 63 - field_idx;
1014 if (inset & (1ULL << bit_idx))
1039 bit_idx = 63 - field_idx;
1040 *inset = *inset | (1ULL << bit_idx);
1064 bit_idx = 63 - field_idx;
1065 *inset = *inset & ~(1ULL << bit_idx);